Design Considerations of Die-Stacked DRAM Caches
- Multiple-channel die-stacked DRAMs have been used for maximizing the performance and minimizing the power of memory access in 2.5D/3D system chips. Stacked DRAM dies can be used as a cache for the processor die in 2.5D/3D system chips. Typically, modern processor system-on-chips (SOCs) have three-level caches, L1, L2, and L3. Could the DRAM cache be used to replace which level of caches? In this paper, we derive an inequality which can aid the designer to check if the designed DRAM cache can provide better performance than the L3 cache. Also, design considerations of DRAM caches for meet the inequality are discussed. We find that a dilemma of the DRAM cache access time and associativity exists for providing better performance than the L3 cache. Organizing multiple channels into a DRAM cache is proposed to cope with the dilemma.
Author: | Rou-Li Melody Wang, Yun-Chao Yu, Jin-Fu Li |
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URN: | urn:nbn:de:hbz:386-kluedo-43258 |
Document Type: | Conference Proceeding |
Language of publication: | English |
Date of Publication (online): | 2016/03/18 |
Year of first Publication: | 2016 |
Publishing Institution: | Technische Universität Kaiserslautern |
Date of the Publication (Server): | 2016/03/14 |
Tag: | Cache; DRAM |
Page Number: | 2 |
Faculties / Organisational entities: | Kaiserslautern - Fachbereich Elektrotechnik und Informationstechnik |
CCS-Classification (computer science): | B. Hardware / B.3 MEMORY STRUCTURES / B.3.1 Semiconductor Memories (NEW) (B.7.1) / Dynamic memory (DRAM) (NEW) |
DDC-Cassification: | 6 Technik, Medizin, angewandte Wissenschaften / 621.3 Elektrotechnik, Elektronik |
Collections: | International Workshop on Emerging Memory Solutions |
Licence (German): | Standard gemäß KLUEDO-Leitlinien vom 30.07.2015 |