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Enabling Low Leakage SRAM Memories at system level: A case study
- In this paper, we show the feasibility of low supply voltage for SRAM (Static Random Access Memory) by adding error correction coding (ECC). In SRAM, the memory matrix needs to be powered for data retentive standby operation, resulting in standby leakage current. Particularly for low duty- cycle systems, the energy consumed due to standby leakage current can become significant. Lowering the supply voltage (VDD) during standby mode to below the specified data retention voltage (DRV) helps decrease the leakage current. At these VDD levels errors start to appear, which we can remedy by adding ECC. We show in this paper that addition of a simple single error correcting (SEC) ECC enables us to decrease the leakage current by 45% and leakage power by 72%. We verify this on a large set of commercially available standard 40nm SRAMs.
Author: | Nur Engin, Ajay Kapoor |
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URN: | urn:nbn:de:hbz:386-kluedo-43040 |
Parent Title (English): | 1st Intl. Workshop on Emerging Memory Solutions |
Document Type: | Conference Proceeding |
Language of publication: | English |
Date of Publication (online): | 2016/03/18 |
Year of first Publication: | 2016 |
Publishing Institution: | Technische Universität Kaiserslautern |
Date of the Publication (Server): | 2016/02/24 |
Tag: | Data retention voltage (DRV); Error correcting coding (ECC); Hamming code; Low leakage; SECDED; SRAM |
Page Number: | 6 |
Faculties / Organisational entities: | Kaiserslautern - Fachbereich Elektrotechnik und Informationstechnik |
CCS-Classification (computer science): | B. Hardware / B.3 MEMORY STRUCTURES / B.3.0 General |
DDC-Cassification: | 6 Technik, Medizin, angewandte Wissenschaften / 621.3 Elektrotechnik, Elektronik |
Collections: | International Workshop on Emerging Memory Solutions |
Licence (German): | Standard gemäß KLUEDO-Leitlinien vom 30.07.2015 |