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A counter-based read circuit tolerant to process variation for low-voltage operating STT-MRAM

  • The capacity of embedded memory on LSIs has kept increasing. It is important to reduce the leakage power of embedded memory for low-power LSIs. In fact, the ITRS predicts that the leakage power in embedded memory will account for 40% of all power consumption by 2024 [1]. A spin transfer torque magneto-resistance random access memory (STT-MRAM) is promising for use as non-volatile memory to reduce the leakage power. It is useful because it can function at low voltages and has a lifetime of over 1016 write cycles [2]. In addition, the STT-MRAM technology has a smaller bit cell than an SRAM. Making the STT-MRAM is suitable for use in high-density products [3–7]. The STT-MRAM uses magnetic tunnel junction (MTJ). The MTJ has two states: a parallel state and an anti-parallel state. These states mean that the magnetization direction of the MTJ’s layers are the same or different. The directions pair determines the MTJ’s magneto- resistance value. The states of MTJ can be changed by the current flowing. The MTJ resistance becomes low in the parallel state and high in the anti-parallel state. The MTJ potentially operates at less than 0.4 V [8]. In other hands, it is difficult to design peripheral circuitry for an STT-MRAM array at such a low voltage. In this paper, we propose a counter-based read circuit that functions at 0.4 V, which is tolerant of process variation and temperature fluctuation.

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Metadaten
Verfasserangaben:Yohei Umeki, Koji Yanagida, Hiroaki Kurotsu, Hiroto Kitahara, Haruki Mori, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Shusuke Yoshimoto
URN (Permalink):urn:nbn:de:hbz:386-kluedo-43224
Dokumentart:Konferenzveröffentlichung
Sprache der Veröffentlichung:Englisch
Veröffentlichungsdatum (online):18.03.2016
Jahr der Veröffentlichung:2016
Veröffentlichende Institution:Technische Universität Kaiserslautern
Datum der Publikation (Server):14.03.2016
Freies Schlagwort / Tag:STT-MRAM
Seitenzahl:2
Fachbereiche / Organisatorische Einheiten:Fachbereich Elektrotechnik und Informationstechnik
CCS-Klassifikation (Informatik):B. Hardware / B.3 MEMORY STRUCTURES / B.3.1 Semiconductor Memories (NEW) (B.7.1)
DDC-Sachgruppen:6 Technik, Medizin, angewandte Wissenschaften / 621.3 Elektrontechnik, Elektronik
Sammlungen:International Workshop on Emerging Memory Solutions
Lizenz (Deutsch):Standard gemäß KLUEDO-Leitlinien vom 30.07.2015