This study presents an energy-efficient ultra-low voltage standard-cell based memory in 28nm FD-SOI. The storage element (standard-cell latch) is replaced with a full- custom designed latch with 50 % less area. Error-free operation is demonstrated down to 450mV @ 9MHz. By utilizing body bias (BB) @ VDD = 0.5 V performance spans from 20 MHz @ BB=0V to 110MHz @ BB=1V.
3D integration of solid-state memories and logic, as demonstrated by the Hybrid Memory Cube (HMC), offers major opportunities for revisiting near-memory computation and gives new hope to mitigate the power and performance losses caused by the “memory wall”. In this paper we present the first exploration steps towards design of the Smart Memory Cube (SMC), a new Processor-in-Memory (PIM) architecture that enhances the capabilities of the logic-base (LoB) in HMC. An accurate simulation environment has been developed, along with a full featured software stack. All offloading and dynamic overheads caused by the operating system, cache coherence, and memory management are considered, as well. Benchmarking results demonstrate up to 2X performance improvement in comparison with the host SoC, and around 1.5X against a similar host-side accelerator. Moreover, by scaling down the voltage and frequency of PIM’s processor it is possible to reduce energy by around 70% and 55% in comparison with the host and the accelerator, respectively.
Memory accesses are the bottleneck of modern computer systems both in terms of performance and energy. This barrier, known as "the Memory Wall", can be break by utilizing memristors. Memristors are novel passive electrical components with varying resistance based on the charge passing through the device . In this abstract, the term "memristor" covers also an extension of the definition, memristive devices, which vary their resistance depending on a state variable . While memristors are naturally used as memory cells, they can also be used for other applications, such as logic circuits .
We present a novel architecture that redefines the relationship between the memory and the processor by enabling data processing within the memory itself. Our architecture is based on a memristive memory array, in which we perform two basic logic operations: Imply (material implication)  and False.
Three-dimensional (3D) integration using through- silicon via (TSV) has been used for memory designs. Content addressable memory (CAM) is an important component in digital systems. In this paper, we propose an evaluation tool for 3D CAMs, which can aid the designer to explore the delay and power of various partitioning strategies. Delay, power, and energy models of 3D CAM with respect to different architectures are built as well.
In this paper, we show the feasibility of low supply voltage for SRAM (Static Random Access Memory) by adding error correction coding (ECC). In SRAM, the memory matrix needs to be powered for data retentive standby operation, resulting in standby leakage current. Particularly for low duty- cycle systems, the energy consumed due to standby leakage current can become significant. Lowering the supply voltage (VDD) during standby mode to below the specified data retention voltage (DRV) helps decrease the leakage current. At these VDD levels errors start to appear, which we can remedy by adding ECC. We show in this paper that addition of a simple single error correcting (SEC) ECC enables us to decrease the leakage current by 45% and leakage power by 72%. We verify this on a large set of commercially available standard 40nm SRAMs.
Emerging Memories (EMs) could benefit from Error Correcting Codes (ECCs) able to correct few errors in a few nanoseconds. The low latency is necessary to meet the DRAM- like and/or eXecuted-in-Place requirements of Storage Class Memory devices. The error correction capability would help manufacturers to cope with unknown failure mechanisms and to fulfill the market demand for a rapid increase in density. This paper shows the design of an ECC decoder for a shortened BCH code with 256-data-bit page able to correct three errors in less than 3 ns. The tight latency constraint is met by pre-computing the coefficients of carefully chosen Error Locator Polynomials, by optimizing the operations in the Galois Fields and by resorting to a fully parallel combinatorial implementation of the decoder. The latency and the area occupancy are first estimated by the number of elementary gates to traverse, and by the total number of elementary gates of the decoder. Eventually, the implementation of the solution by Synopsys topographical synthesis methodology in 54nm logic gate length CMOS technology gives a latency lower than 3 ns and a total area less than \(250 \cdot 10^3 \mu m^2\).
This paper briefly discusses a new architecture, Computation-In-Memory (CIM Architecture), which performs “processing-in-memory”. It is based on the integration of storage and computation in the same physical location (crossbar topology) and the use of non-volatile resistive-switching technology (memristive devices or memristors in short) instead of CMOS technology. The architecture has the potential of improving the energy-delay product, computing efficiency and performance area by at least two orders of magnitude.
In the Iranian public media, it was widely reported that by the end of 2004, 380 hectares of the eastern farthest end of the Peninsula Mianqala (northern part of Iran, located in the southeastern coasts of Caspian Sea) were sold to an organisation – the result is that "Asurada" Island will be turned into a so-called “Tourist Village”. The decision has been made and civil works are to begin. The village planned as a new settlement is specifically considered to work with Mianqala, which since June 1976 is an international biosphere reserve and since 1969, an Iranian nature protected area. Considering the special condition of the region as a biosphere reserve, this paper introduces the current situation of the Island Āŝūrāda and the suggested program by the aforementioned organisation. Subsequently, it tries to find an optimal answer to the question of whether "Āŝūrāda" is appropriate for such a purpose and how far it is allowed to be interfered with, through this new settlement. The paper asserts for this development, there is consideration of the settlement’s urban and architectural concept; subsequently analysis is conducted for the spatial development of the settlement, in terms of its influences on the ecological sources, the rural structure and the financial as well as social aspects. Such study is required, particularly due to the chain of tourist influences, which certainly will introduce a new pattern of urban character in terms of quality and quantity. Finally, with the assistance of the case presented, this paper poses the question of whether a new urban pattern like this can endanger a traditional and above all a nature protected context or not.
This Essay considers the motives and the formation of European New Towns, in particular German ones. For this reason it studies basically the development of German New towns, further defines the German classification of this urban term. This essay suggests additionally for this sense a kind of classification in Germany – considering to periodical as well as formal progress of German New towns. All suggested classes are specifically and individually recognized and introduced, for each one is also given specific examples. Each case is furthermore introduced and it’s motive of formation and development are considered as well, e.g. cities like Ludwigshafen, Hellerau, Wolfsburg, Wulfen. Regarding to the development of German New Towns and up to the given facts in the essay, the current and the expected situation of German New towns are finally considered, also the sense of German experiences for Iranian New towns, and it’s possible significance for them.
Langvorträge: T. Schorr, A. Dittrich, W. Sauer-Greff, R. Urbansky (Lehrstuhl für Nachrichtentechnik, TU Kaiserslautern): Iterative Equalization in Fibre Optical Systems Using High-Rate RCPR, BCH and LDPC Codes A. Doenmez, T. Hehn, J. B. Huber (Lehrstuhl für Informationsübertragung, Universität Erlangen-Nürnberg): Analytical Calculation of Thresholds for LDPC Codes transmitted over Binary Erasure Channels S. Deng, T. Weber (Institut für Nachrichtentechnik und Informationselektronik, Universität Rostock), M. Meurer (Lehrstuhl für hochfrequente Signalübertragung und -verarbeitung, TU Kaiserslautern): Dynamic Resource Allocation in Future OFDM Based Mobile Radio Systems J. Hahn, M. Meurer, T. Weber (Lehrstuhl für hochfrequente Signalübertragung und -verarbeitung, TU Kaiserslautern): Receiver Oriented FEC Coding (RFC) for Selective Channels C. Stierstorfer, R. Fischer (Lehrstuhl für Informationsübertragung, Universität Erlangen-Nürnberg): Comparison of Code Design Requirements for Single- and Multicarrier Transmission over Frequency-Selective MIMO Channels A. Scherb (Arbeitsbereich Nachrichtentechnik, Universität Bremen): Unbiased Semiblind Channel Estimation for Coded Systems T.-J. Liang, W. Rave, G. Fettweis (Vodafone Stiftungslehrstuhl Mobile Nachrichtensysteme, Technische Universität Dresden): Iterative Joint Channel Estimation and Decoding Using Superimposed Pilots in OFDM-WLAN A. Dittrich, T. Schorr, W. Sauer-Greff, R. Urbansky (Lehrstuhl für Nachrichtentechnik, TU Kaiserslautern): DIORAMA - An Iterative Decoding Real-Time MATLAB Receiver for the Multicarrier-Based Digital Radio DRM Kurzvorträge: S. Plass, A. Dammann (German Aerospace Center (DLR)): Radio Resource Management for MC-CDMA over Correlated Rayleigh Fading Channels S. Heilmann, M. Meurer, S. Abdellaoui, T. Weber (Lehrstuhl für hochfrequente Signalübertragung und -verarbeitung, TU Kaiserslautern): Concepts for Accurate Low-Cost Signature Based Localisation of Mobile Terminals M. Siegrist, A. Dittrich, W. Sauer-Greff, R. Urbansky (Lehrstuhl für Nachrichtentechnik, TU Kaiserslautern): SIMO and MIMO Concepts for Fibre Optical Communications C. Bockelmann (Arbeitsbereich Nachrichtentechnik, Universität Bremen): Sender- und Empfängerstrukturen für codierte MIMO-Übertragung