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We present a detailed analysis of a scalar conformal four-point function obtained from AdS/CFT correspondence. We study the scalar exchange graphs in AdS and discuss their analytic properties. Using methods of conformal partial wave analysis, we present a general procedure to study conformal four-point functions in terms of exchanges of scalar and tensor fields. The logarithmic terms in the four-point functions are connected to the anomalous dimensions of the exchanged fields. Comparison of the results from AdS graphs with the conformal partial wave analysis, suggests a possible general form for the operator product expansion of scalar fields in the boundary CFT.

We discuss the analytic properties of AdS scalar exchange graphs in the crossed channel. We show that the possible non-analytic terms drop out by virtue of non-trivial properties of generalized hypergeometric functions. The absence of non-analytic terms is a necessary condition for the existence of an operator product expansion for CFT amplitudes obtained from AdS/CFT correspondence.

Emerging Memories (EMs) could benefit from Error Correcting Codes (ECCs) able to correct few errors in a few nanoseconds. The low latency is necessary to meet the DRAM- like and/or eXecuted-in-Place requirements of Storage Class Memory devices. The error correction capability would help manufacturers to cope with unknown failure mechanisms and to fulfill the market demand for a rapid increase in density. This paper shows the design of an ECC decoder for a shortened BCH code with 256-data-bit page able to correct three errors in less than 3 ns. The tight latency constraint is met by pre-computing the coefficients of carefully chosen Error Locator Polynomials, by optimizing the operations in the Galois Fields and by resorting to a fully parallel combinatorial implementation of the decoder. The latency and the area occupancy are first estimated by the number of elementary gates to traverse, and by the total number of elementary gates of the decoder. Eventually, the implementation of the solution by Synopsys topographical synthesis methodology in 54nm logic gate length CMOS technology gives a latency lower than 3 ns and a total area less than \(250 \cdot 10^3 \mu m^2\).