Due to the steadily increasing number of decentralized generation units, the upcoming smart meter rollout and the expected electrification of the transport sector (e-mobility), grid planning and grid operation at low-voltage (LV) level are facing major challenges. Therefore, many studies, research and demonstration projects on the above topics have been carried out in recent years, and the results and the methods developed have been published. However, the published methods usually cannot be replicated or validated, since the majority of the examination models or the scenarios used are incomprehensible to third parties. There is a lack of uniform grid models that map the German LV grids and can be used for comparative investigations, which are similar to the example of the North American distribution grid models of the IEEE. In contrast to the transmission grid, whose structure is known with high accuracy, suitable grid models for LV grids are difficult to map because of the high number of LV grids and distribution system operators. Furthermore, a detailed description of real LV grids is usually not available in scientific publications for data privacy reasons. For investigations within a research project, the most characteristic synthetic LV grid models have been created, which are based on common settlement structures and usual grid planning principles in Germany. In this work, these LV grid models, and their development are explained in detail. For the first time, comprehensible LV grid models for the middle European area are available to the public, which can be used as a benchmark for further scientific research and method developments. This document is an English version of the paper which was originally written in German1. In addition, this paper discusses a few more aspects especially on the planning process of distribution grids in Germany.

Beamforming performs spatial filtering to preserve the signal from given directions of interest while suppressing interfering signals and noise arriving from other directions. For example, a microphone array equipped with beamforming algorithm could preserve the sound coming from a target speaker and suppress sounds coming from other speakers. Beamformer has been widely used in many applications such as radar, sonar, communication, and acoustic systems. A data-independent beamformer is the beamformer whose coefficients are independent on sensor signals, it normally uses less computation since the coefficients are computed once. Moreover, its coefficients are derived from the well-defined statistical models, then it produces less artifacts. The major drawback of this beamforming class is its limitation to the interference suppression. On the other hand, an adaptive beamformer is a beamformer whose coefficients depend on or adapt to sensor signals. It is capable of suppressing the interference better than a data-independent beamforming but it suffers from either too much distortion of the signal of interest or less noise reduction when the updating rate of coefficients does not synchronize with the changing rate of the noise model. Besides, it is computationally intensive since the coefficients need to be updated frequently. In acoustic applications, the bandwidth of signals of interest extends over several octaves, but we always expect that the characteristic of the beamformer is invariant with regard to the bandwidth of interest. This can be achieved by the so-called broadband beamforming. Since the beam pattern of conventional beamformers depends on the frequency of the signal, it is common to use a dense and uniform array for the broadband beamforming to guarantee some essential performances together, such as frequency-independence, less sensitive to white noise, high directivity factor or high front-to-back ratio. In this dissertation, we mainly focus on the sparse array of which the aim is to use fewer sensors in the array, while simultaneously assuring several important performances of the beamformer. In the past few decades, many design methodologies for sparse arrays have been proposed and were applied in a variety of practical applications. Although good results were presented, there are still some restrictions, such as the number of sensors is large, the designed beam pattern must be fixed, the steering ability is limited and the computational complexity is high. In this work, two novel approaches for the sparse array design taking a hypothesized uniform array as a basis are proposed, that is, one for data-independent beamformers and the another for adaptive beamformers. As an underlying component of the proposed methods, the dissertation introduces some new insights into the uniform array with broadband beamforming. In this context, a function formulating the relations between the sensor coefficients and its beam pattern over frequency is proposed. The function mainly contains the coordinate transform and inverse Fourier transform. Furthermore, from the bijection of the function and broadband beamforming perspective, we propose the lower and upper bounds for the inter-distance of sensors. Within these bounds, the function is a bijective function that can be utilized to design the uniform array with broadband beamforming. For data-independent beamforming, many studies have focused on optimization procedures to seek the sparse array deployment. This dissertation presents an alternative approach to determine the location of sensors. Starting with a weight spectrum of a virtual dense and uniform array, some techniques are used, such as analyzing a weight spectrum to determine the critical sensors, applying the clustering technique to group the sensors into different groups and selecting representative sensors for each group. After the sparse array deployment is specified, the optimization technique is applied to find the beamformer coefficients. The proposed method helps to save the computation time in the design phase and its beamformer performance outperforms other state-of-the-art methods in several aspects such as the higher white noise gain, higher directivity factor or more frequency-independence. For adaptive beamforming, the dissertation attempts to design a versatile sparse microphone array that can be used for different beam patterns. Furthermore, we aim to reduce the number of microphones in the sparse array while ensuring that its performance can continue to compete with a highly dense and uniform array in terms of broadband beamforming. An irregular microphone array in a planar surface with the maximum number of distinct distances between the microphones is proposed. It is demonstrated that the irregular microphone array is well-suited to sparse recovery algorithms that are used to solve underdetermined systems with subject to sparse solutions. Here, a sparse solution is the sound source's spatial spectrum that need to be reconstructed from microphone signals. From the reconstructed sound sources, a method for array interpolation is presented to obtain an interpolated dense and uniform microphone array that performs well with broadband beamforming. In addition, two alternative approaches for generalized sidelobe canceler (GSC) beamformer are proposed. One is the data-independent beamforming variant, the other is the adaptive beamforming variant. The GSC decomposes beamforming into two paths: The upper path is to preserve the desired signal, the lower path is to suppress the desired signal. From a beam pattern viewpoint, we propose an improvement for GSC, that is, instead of using the blocking matrix in the lower path to suppress the desired signal, we design a beamformer that contains the nulls at the look direction and at some other directions. Both approaches are simple beamforming design methods and they can be applied to either sparse array or uniform array. Lastly, a new technique for direction-of-arrival (DOA) estimation based on the annihilating filter is also presented in this dissertation. It is based on the idea of finite rate of innovation to reconstruct the stream of Diracs, that is, identifying an annihilating filter/locator filter for a few uniform samples and the position of the Diracs are then related to the roots of the filter. Here, an annihilating filter is the filter that suppresses the signal, since its coefficient vector is always orthogonal to every frame of signal. In the DOA context, we regard an active source as a Dirac associated with the arrival direction, then the directions of active sources can be derived from the roots of the annihilating filter. However, the DOA obtained by this method is sensitive to noise and the number of DOAs is limited. To address these issues, the dissertation proposes a robust method to design the annihilating filter and to increase the degree-of-freedom of the measurement system (more active sources can be detected) via observing multiple data frames. Furthermore, we also analyze the performance of DOA with diffuse noise and propose an extended multiple signal classification algorithm that takes diffuse noise into account. In the simulation, it shows, that in the case of diffuse noise, only the extended multiple signal classification algorithm can estimate the DOAs properly.

We introduce Property-Driven Design, a tool-flow that guarantees formal soundness be- tween ESL and RTL and thus enables a shift-left of general functional verification by moving HW verification to higher abstraction layers. In addition, by generating a formal Verification IP (VIP) automatically from ESL descriptions, the entry hurdle to formal methods is reduced considerably, opening them to a wider audience, which effectively ‘democratizes’ them. Short feedback cycles reduce time spent on RTL verification and lead to higher-quality designs.

Bees are recognized as an indispensable link in the human food chain and general ecological system. Numerous threats, from pesticides to parasites, endanger bees and frequently lead to hive collapse. The varroa destructor mite is a key threat to bee keeping and the monitoring of hive infestation level is of major concern for effective treatment. Sensors and automation, e.g., as in condition-monitoring and Industry 4.0, with machine learning offer help. In numerous activities a rich variety of sensors have been applied to apiary/hive instrumentation and bee monitoring. Quite recent activities try to extract estimates of varroa infestation level by hive air analysis based on gas sensing and gas sensor systems. In our work in the IndusBee4.0 project [8, 11], an hive-integrated, compact autonomous gas sensing system for varroa infestation level estimation based on low- cost highly integrated gas sensors was conceived and applied. This paper adds to [11] with the first results of a mid-term duration investigation from July to September 2020 until formic acid treatment. For the regarded hive more than 79 % of detection probability based on the SGP30 gas sensor readings have been achieved.

Code coverage analysis plays an important role in the software testing process. More recently, the remarkable effectiveness of coverage feedback has triggered a broad interest in feedback-guided fuzzing. In this work, we discuss static instrumentation techniques for binary-level coverage analysis without compiler support. We show that the proposed techniques are precise, efficient, and transparent significantly beyond the state of the art. We implement these techniques into two tools, namely, Spedi and bcov. Both tools are open source and publicly available. Spedi shows that the disassembly and function identification of stripped binaries can be highly accurate without resort to any external information. We build on these important results in bcov where we statically instrument x86-64 ELF binaries to track code coverage. However, improving efficiency and scaling to large real-world software required an orchestrated effort combining several techniques. First, we bring a well-known probe pruning technique, for the first time, to binary-level instrumentation and effectively leverage its notion of superblocks to reduce overhead. Second, we introduce sliced microexecution, a robust technique for jump table analysis which improves CFG precision and enables us to instrument jump table entries. Additionally, smaller instructions in x86-64 pose a challenge for inserting detours. To address this challenge, we aggressively exploit padding bytes. Also, we introduce a greedy scheme to systematically host detours in neighboring basic blocks. We evaluate bcov on a corpus of 95 binaries compiled from eight popular and well-tested packages like FFmpeg and LLVM. Two instrumentation policies, with different edge-level precision, are used to patch all functions in this corpus - over 1.6 million functions. Our precise policy has average performance and memory overheads of 14% and 22%, respectively. Instrumented binaries do not introduce any test regressions. The reported coverage is highly accurate with an average F-score of 99.86%. Finally, our jump table analysis is comparable to that of IDA Pro on gcc binaries and outperforms it on clang binaries. Our work demonstrates that static instrumentation can offer unique advantages in comparison to established methods like compiler instrumentation and dynamic binary instrumentation. It also opens the door for many interesting applications of static instrumentation, which can go well beyond coverage analysis.

Mit dem Vorhandensein elektrischer Energie und moderner Sensorik an elektrisch unterstützten Fahrrädern eröffnen sich neue Möglichkeiten der Entwicklung von Fahrerassistenzsystemen am Pedelec zur Erhöhung der Sicherheit und des Fahrkomforts. Die Leistungsfähigkeit solcher Systeme kann durch die Nutzung von Inertialsensorik weiter gesteigert werden. Jedoch müssen solche Sensoren, vor allem bei sicherheitsrelevanten Assistenzsystemen, zuverlässige, robuste und plausible Sensordaten liefern. Hieraus ergibt sich das Thema dieser Arbeit: die Evaluation von Inertialsensorik für Fahrerassistenzsysteme am Pedelec anhand systematischer Untersuchung der Fahrdynamik. Durch simulative und experimentelle Untersuchungen der MEMS-Sensorik und der Fahrdynamik, basierend auf Testkatalogen, werden die Anforderungen an Inertialsensorik abgeleitet und die Störbarkeit der Drehrate analysiert. Dabei führt die Betrachtung verschiedener Sensortypen, Fahrszenarien und Anbaupositionen zu der Erkenntnis, dass bspw. die Anbauposition am Sattelrohr und in der Antriebseinheit besonders geeignet sind. Vor allem der betrachtete Automotive-MEMS-Sensor liefert auch bei potentiell kritischen Vibrationen bei einer Fahrt über Kopfsteinpflaster oder über Treppenstufen sowie bei Bremsenquietschen zuverlässig plausible Sensordaten. Zusätzlich zeigt eine Betrachtung der Auswirkungen von Sensorfehlern auf eine Datenfusion, d.h. der Berechnung der Raumwinkel, dass vor allem die Minimierung des Offset-Fehlers, bspw. durch eine Langzeitkorrektur, sinnvoll erscheint und resultierende Winkelfehler minimieren kann. Die Untersuchung der Fahrdynamik betrachtet insbesondere das Fahrszenario (kritische) Kurvenfahrt. Anhand der Fahrdaten zahlreicher Pedelec-Nutzer werden eine Methode zur Erkennung von Kurvenfahrten sowie theoretische Ansätze zur Vermeidung einer kritischen Kurvenfahrt durch einen aktiven Lenkeingriff realisiert.

Multicore processors and Multiprocessor System-on-Chip (MPSoC) have become essential in Real-Time Systems (RTS) and Mixed-Criticality Systems (MCS) because of their additional computing capabilities that help reduce Size, Weight, and Power (SWaP), required wiring, and associated costs. In distributed systems, a single shared multicore or MPSoC node executes several applications, possibly of different criticality levels. However, there is interference between applications due to contention in shared resources such as CPU core, cache, memory, and network. Existing allocation and scheduling methods for RTS and MCS often rely on implicit assumptions of the constant availability of individual resources, especially the CPU, to provide guaranteed progress of tasks. Most existing approaches aim to resolve contention in only a specific shared resource or a set of specific shared resources. Moreover, they handle a limited number of events such as task arrivals and task completions. In distributed RTS and MCS with several nodes, each having multiple resources, if the applications, resource availability, or system configurations change, obtaining assumptions about resources becomes complicated. Thus, it is challenging to meet end-to-end constraints by considering each node, resource, or application individually. Such RTS and MCS need global resource management to coordinate and dynamically adapt system-wide allocation of resources. In addition, the resource management can dynamically adapt applications to changing availability of resources and maintains a system-wide (global) view of resources and applications. The overall aim of global resource management is twofold. Firstly, it must ensure real-time applications meet their end-to-end deadlines even in the presence of faults and changing environmental conditions. Secondly, it must provide efficient resource utilization to improve the Quality of Service (QoS) of co-executing Best-Effort (BE) (or non-critical) applications. A single fault in global resource management can render it useless. In the worst case, the resource management can make faulty decisions leading to a deadline miss in real-time applications. With the advent of Industry 4.0, cloud computing, and Internet-of-Things (IoT), it has become essential to combine stringent real-time constraints and reliability requirements with the need for an open-world assumption and ensure that the global resource management does not become an inviting target for attackers. In this dissertation, we propose a domain-independent global resource management framework for distributed RTS and MCS consisting of heterogeneous nodes based on multicore processors or MPSoC. We initially developed the framework with the French Aerospace Lab -- ONERA and Thales Research & Technology during the DREAMS project and later extended it during SECREDAS and other internal projects. Unlike previous resource management frameworks RTS and MCS, we consider both safety and security for the framework itself. To enable real-time industries to use cloud computing and enter a new market segment -- real-time operation as a cloud-based service, we propose a Real-Time-Cloud (RT-Cloud) based on global resource management for hosting RTS and MCS. Finally, we present a mixed-criticality avionics use case for evaluating the capabilities of the global resource management framework in handling permanent core failures and temporal overload condition, and a railway use case to motivate the use of RT-Cloud with global resource management.

Ethernet has become an established communication technology in industrial automation. This was possible thanks to the tremendous technological advances and enhancements of Ethernet such as increasing the link-speed, integrating the full-duplex transmission and the use of switches. However these enhancements were still not enough for certain high deterministic industrial applications such as motion control, which requires cycle time below one millisecond and jitter or delay deviation below one microsecond. To meet these high timing requirements, machine and plant manufacturers had to extend the standard Ethernet with real-time capability. As a result, vendor-specific and non-IEEE standard-compliant "Industrial Ethernet" (IE) solutions have emerged. The IEEE Time-Sensitive Networking (TSN) Task Group specifies new IEEE-conformant functionalities and mechanisms to enable the determinism missing from Ethernet. Standard-compliant systems are very attractive to the industry because they guarantee investment security and sustainable solutions. TSN is considered therefore to be an opportunity to increase the performance of established Industrial-Ethernet systems and to move forward to Industry 4.0, which require standard mechanisms. The challenge remains, however, for the Industrial Ethernet organizations to combine their protocols with the TSN standards without running the risk of creating incompatible technologies. TSN specifies 9 standards and enhancements that handle multiple communication aspects. In this thesis, the evaluation of the use of TSN in industrial real-time communication is restricted to four deterministic standards: IEEE802.1AS-Rev, IEEE802.1Qbu IEEE802.3br and IEEE802.1Qbv. The specification of these TSN sub-standards was finished at an early research stage of the thesis and hardware prototypes were available. Integrating TSN into the Industrial-Ethernet protocols is considered a substantial strategical challenge for the industry. The benefits, limits and risks are too complex to estimate without a thorough investigation. The large number of Standard enhancements makes it hard to select the required/appropriate functionalities. In order to cover all real-time classes in the automation [9], four established Industrial-Ethernet protocols have been selected for evaluation and combination with TSN as well as other performance relevant communication features. The objectives of this thesis are to (1) Provide theoretical, simulation and experimental evaluation-methodologies for the timing performance analysis of the deterministic TSN-standards mentioned above. Multiple test-plans are specified to evaluate the performance and compatibility of early version TSN-prototypes from different providers. (2) Investigate multiple approaches and deduce migration strategies to integrate these features into the established Industrial-Ethernet protocols: Sercos III, Profinet IRT, Profinet RT and Ethernet/IP. A scenario of coexistence of time-critical traffic with other traffic in a TSN-network proves that the timing performance for highly deterministic applications, e.g. motion-control, can only be guaranteed by the TSN scheduling algorithm IEEE802.1Qbv. Based on a requirements survey of highly deterministic industrial applications, multiple network scenarios and experiments are presented. The results are summarized into two case studies. The first case study shows that TSN alone is not enough to meet these requirements. The second case study investigates the benefits of additional mechanisms (Gigabit link-speed, minimum cycle time modeling, frame forwarding mechanisms, frame structure, topology migration, etc.) in combination with the TSN features. An implementation prototype of the proposed system and a simulation case study are used for the evaluation of the approach. The prototype is used for the evaluation and validation of the simulation model. Due to given scalability constraints of the prototype (no cut-through functionalities, limited number of TSN-prototypes, etc…), a realistic simulation model, using the network simulation tool OMNEST / OMNeT++, is conducted. The obtained evaluation results show that a minimum cycle time ≤1 ms and a maximum jitter ≤1 μs can be achieved with the presented approaches.

Durch den wachsenden Anteil an Erzeugungsanlagen und leistungsstarken Verbrauchern aus dem Verkehr- und Wärmesektor kommen Niederspannungsnetze immer näher an ihre Betriebsgrenzen. Da für die Niederspannungsnetze bisher keine Messwerterfassung vorgesehen war, können Netzbetreiber Grenzverletzungen nicht erkennen. Um dieses zu ändern, werden deutsche Anschlussnutzer in Zukunft flächendeckend mit modernen Messeinrichtungen oder intelligenten Messsystemen (auch als Smart Meter bezeichnet) ausgestattet sein. Diese sind in der Lage über eine Kommunikationseinheit, das Smart-Meter-Gateway, Messdaten an die Netzbetreiber zu senden. Werden Messdaten aber als personenbezogene Netzzustandsdaten deklariert, so ist aus Datenschutzgründen eine Erhebung dieser Daten weitgehend untersagt. Ziel dieser Arbeit ist es eine Zustandsschätzung zu entwickeln, die auch bei niedrigredundanter Messwertaufnahme für den Netzbetrieb von Niederspannungsnetzen anwendbare Ergebnisse liefert. Neben geeigneten Algorithmen zur Zustandsschätzung ist dazu die Generierung von Ersatzwerten im Fokus. Die Untersuchungen und Erkenntnisse dieser Arbeit tragen dazu bei, den Verteilnetzbetreibern bei den maßgeblichen Entscheidungen in Bezug auf die Zustandsschätzung in Niederspannungsnetzen zu unterstützen. Erst wenn Niederspannungsnetze mit Hilfe der Zustandsschätzung beobachtbar sind, können darauf aufbauende Konzepte zur Regelung entwickelt werden, um die Energiewende zu unterstützen.

In dieser Arbeit wird ein formales Modell zur Beschreibung von hardwarenaher Software vorgestellt: Die Programmnetzliste. Die Programmnetzliste (PN) besteht aus Instruktionszellen die in einem gerichteten azyklischen Graph verbunden sind und dabei alle Ausführungspfade des betrachteten Programms beinhaltet. Die einzelnen Instruktionszellen repräsentieren eine Instruktion oder eine Instruktionssequenz. Die PN verfügt über eine explizite Darstellung des Programmablaufs und eine implizite Modellierung des Datenpfads und ist als Modell für die Verifikation von Software nutzbar. Die Software wird dabei auf Maschinencode-Level betrachtet. Die Modellgenerierung besteht aus wenigen und gut automatisierbaren Schritten. Als Grundlage dient ein – ggf. unvollständiger – Kontrollfluss Graph (CFG), der aus der Software generiert werden kann. Die Modellgenerierung besteht aus zwei Schritten. Der erste Schritt ist die Erzeugung des expliziten Programmablaufs, indem der CFG abgerollt wird. Dabei wird ein sogenannter Execution-Graph (EXG) erzeugt, der alle möglichen Ausführungspfade des betrachteten Programms beinhaltet. Um dieses Modell so kompakt wie möglich zu halten, werden unterschiedliche Techniken verwendet – wie das Zusammenführen gemeinsamer Pfade und das Erkennen von “toten” Verzweigungen im Programm, die an der entsprechenden Stelle niemals ausgeführt werden. Im Anschluss wird im zweiten Schritt der Execution-Graph in die Programmnetzliste (PN) übersetzt. Dabei werden alle Knoten im EXG durch eine entsprechende Instruktionszelle ersetzt. Die Kanten des Graphen entsprechen dabei dem Programmzustand. Der Programmzustand setzt sich aus den Variablen im Speicher wie auch dem Architekturzustand des unterliegenden Prozessors zusammen. Ergänzt wird der Programmzustand in der Programmnetzliste um ein sogenanntes Active-Bit, welches es ermöglicht den aktiven Pfad in der Netzliste zu markieren. Das ist notwendig, da die Software immer nur einen Pfad gleichzeitig ausführen kann, aber die PN alle möglichen Pfade beinhaltet. Auf der Programmnetzliste können dann mit Hilfe von Hardware Property Checkern basierend auf BMC oder IPC diverse Eigenschaften bewiesen werden. Zusätzlich wird die Programmnetzliste um die Fähigkeit zur Interruptmodellierung erweitert.

In today’s world, mobile communication has become one of the most widely used technologies corroborated by growing number of mobile subscriptions and extensive usage of mobile multimedia services. It is a key challenge for the network operators to accommodate such large number of users and high traffic volume. Further, several day-to-day scenarios such as public transportation, public events etc., are now characterized with high mobile data usage. A large number of users avail cellular services in such situations posing high load to the respective base stations. This results in increased number of dropped connections, blocking of new access attempts and blocking of handovers (HO). The users in such system will thus be subjected to poor Quality of Experience (QoE). Beforehand knowledge of the changing data traffic dynamics associated with such practical situations will assist in designing radio resource management schemes aiming to ease the forthcoming congestion situations. The key hypothesis of this thesis is that consideration and utilization of additional context information regarding user, network and his environment is valuable in designing such smart Radio Resource Management(RRM) schemes. Methods are developed to predict the user cell transitions, considering the fact that mobility of the users is not purely random but rather direction oriented. This is particularly used in case of traffic dense moving network or group of users moving jointly in the same vehicle (e.g., bus, train, etc.) to predict the propagation of high load situation among cells well in advance. This enables a proactive triggering of load balancing (LB) in cells anticipating the arrival of high load situation and accommodating the incoming user group or moving network. The evaluated KPIs such as blocked access attempts, dropped connections and blocked HO are reduced. Further, everyday scenario of dynamic crowd formation is considered as another potential case of high load situation. In real world scenarios such as open air festivals, shopping malls, stadiums or public events, several mobile users gather to form a crowd. This poses high load situation to the respective serving base station at the site of crowd formation, thereby leading to congestion. As a consequence, mobile users are subjected to poor QoE due to high dropping and blocking rates. A framework to predict crowd formation in a cell is developed based on coalition of user cell transition prediction, cluster detection and trajectory prediction. This framework is suitably used to prompt context aware load balancing mechanism and activate a small cell at the probable site of crowd formation. Simulations show that proactive LB reduces the dropping of users (23%), blocking of users (10%) and blocked HO (15%). In addition, activation of a Small Cell (SC) at the site of frequent crowd formation leads to further reductions in dropping of users (60%), blocking of users (56%) and blocked HO (59%). Similar to the framework for crowd formation prediction, a concept is developed for predicting vehicular traffic jams. Many vehicular users avail broadband cellular services on a daily basis while traveling. The density of such vehicular users change dynamically in a cell and at certain sites (e.g. signal lights), traffic jams arise frequently leading to a high load situation at respective serving base station. A traffic prediction algorithm is developed from cellular network perspective as a coalition strategy consisting of schemes to predict user cell transition, vehicular cluster/moving network detection, user velocity monitoring etc. The traffic status indication provided by the algorithm is then used to trigger LB and activate/deactivate a small cell suitably. The evaluated KPIs such as blocked access attempts, dropped connections and blocked HO are reduced by approximately 10%, 18% and 18%, respectively due to LB. In addition, switching ON of SC reduces blocked access attempts, dropped connections and blocked HO by circa 42%, 82% and 81%, respectively. Amidst increasing number of connected devices and traffic volume, another key issue for today’s network is to provide uniform service quality despite high mobility. Further, urban scenarios are often characterized by coverage holes which hinder service continuity. A context aware resource allocation scheme is proposed which uses enhanced mobility prediction to facilitate service continuity. Mobility prediction takes into account additional information about the user’s origin and possible destination to predict next road segment. If a coverage hole is anticipated in upcoming road, then additional resources are allocated to respective user and data is buffered suitably. The buffered data is used when the user is in a coverage hole to improve service continuity. Simulation shows improvement in throughput (in coverage hole) by circa 80% and service interruption is reduced by around 90%, for a non-real-time streaming service. Additionally, investigation of context aware procedures is carried out with a focus on user mobility, to find commonalities among different procedures and a general framework is proposed to support mobility context awareness. The new information and interfaces which are required from various entities (e.g., vehicular infrastructure) are discussed as well. Device-to-Device (D2D) communications commonly refer to the technology that enables direct communication between devices, hence relieving the base station from traffic routing. Thus, D2D communication is a feasible solution in crowded situations, where users in proximity requesting to communicate with one another could be granted D2D links for communication, thereby easing the traffic load to serving base station. D2D links can potentially reuse the radio resources from cellular users (known as D2D underlay) leading to better spectral utilization. However, the mutual interference can hinder system performance. For instance, if D2D links are reusing cellular uplink resources then D2D transmissions cause interference to cellular uplink at base station. Whereas, cellular transmissions cause interference to D2D receivers. To cope up with such issues, location aware resource allocation schemes are proposed for D2D communication. The key aim of such RA scheme is to reuse resources with minimal interference. The RA scheme based on virtual sectoring of a cell leads to approximately 15% more established links and 25% more capacity with respect to a random resource allocation. D2D transmissions cause significant interference to cellular links with which they reuse physical resource blocks, thereby hindering cellular performance. Regulating D2D transmissions to mitigate the aforementioned problem would mean sub-optimal exploitation of D2D communications. As a solution, post-resource allocation power control at cellular users is proposed. Three schemes namely interference aware power control, blind power control and threshold based power control are discussed. Simulation results show reductions in dropping of cellular users due to interference from D2D transmissions, improvement in throughput at base station (uplink) while not hindering the D2D performance.

Im Gegensatz zum Übertragungsnetz, dessen Struktur hinreichend genau bekannt ist, sind passende Netzmodelle für Mittelspannungsnetze (MS-Netze) wegen der hohen Anzahlen der MS-Netze und Verteilnetzbetreiber (VNB) nur schwer abzubilden. Des Weiteren ist eine detaillierte Darstellung realer MS-Netze in wissenschaftlichen Publikationen aus datenschutzrechtlichen Gründen meist nicht erwünscht. In dieser Arbeit werden MS-Netzmodelle sowie ihre Entwicklung im Detail erklärt. Damit stehen erstmals für die Öffentlichkeit nachvollziehbare MS-Netzmodelle für den deutschsprachigen Raum zur Verfügung. Sie können als Benchmark für wissenschaftliche Untersuchungen sowie zur Methodenentwicklung verwendet werden.

Der zunehmende Ausbau dezentraler Erzeugungsanlagen sowie die steigende Anzahl an Elektrofahrzeugen stellen die Niederspannungsnetze vor neue Herausforderungen. Neben der Einhaltung des zulässigen Spannungsbands führen Erzeugungsanlagen und neue Lasten zu einer zunehmenden thermischen Auslastung der Leitungen. Einfache, konventionelle Maßnahmen wie Topologieänderungen zu vermascht betriebenen Niederspannungsnetzen sind ein erster hilfreicher und kostengünstiger Ansatz, bieten aber keinen grundsätzlichen Schutz vor einer thermischen Überlastung der Betriebsmittel. Diese Arbeit befasst sich mit der Konzeption eines Spannungs- und Wirkleistungsreglers für vermaschte Niederspannungsnetze. Durch den Regler erfolgt eine messtechnische Erfassung der Spannungen und Ströme in einzelnen Messpunkten des Niederspannungsnetzes. Mit Hilfe eines speziellen Kennlinienverfahrens kann eine Leistungsverschiebung in einzelnen Netzmaschen hervorgerufen und vorgegebene Soll- oder Grenzwerte eingehalten werden. In vorliegender Arbeit werden die analytischen Grundlagen des Reglers, seine Hardware sowie das Kennlinienverfahren zusammen mit den realisierbaren Regelkonzepten vorgestellt. Die Ergebnisse aus Simulationsstudien, Labor- und Feldtests stellen die Effektivität des Reglers eindeutig dar und werden diskutiert.

The fifth-generation mobile telecommunication network is expected to support multi-access edge computing (MEC), which intends to distribute computation tasks and services from the central cloud to the edge clouds. Toward ultra-responsive, ultra-reliable, and ultra-low-latency MEC services, the current mobile network security architecture should enable a more decentralized approach for authentication and authorization processes. This paper proposes a novel decentralized authentication architecture that supports flexible and low-cost local authentication with the awareness of context information of network elements such as user equipment and virtual network functions. Based on a Markov model for backhaul link quality as well as a random walk mobility model with mixed mobility classes and traffic scenarios, numerical simulations have demonstrated that the proposed approach is able to achieve a flexible balance between the network operating cost and the MEC reliability.

Radar cross section reducing (RCSR) metasurfaces or coding metasurfaces were primarily designed for normally incident radiation in the past. It is evident that the performance of coding metasurfaces for RCSR can be significantly improved by additional backscattering reduction of obliquely incident radiation, which requires a valid analytic conception tool. Here, we derive an analytic current density distribution model for the calculation of the backscatter far-field of obliquely incident radiation on a coding metasurface for RCSR. For demonstration, we devise and fabricate a metasurface for a working frequency of 10.66GHz and obtain good agreement between the measured, simulated, and analytically calculated backscatter far-fields. The metasurface significantly reduces backscattering for incidence angles between −40∘ and 40∘ in a spectral working range of approximately 1GHz.

The complexity of modern real-time systems is increasing day by day. This inevitable rise in complexity predominantly stems from two contradicting requirements, i.e., ever increasing demand for functionality, and required low cost for the final product. The development of modern multi-processors and variety of network protocols and architectures have enabled such a leap in complexity and functionality possible. Albeit, efficient use of these multi-processors and network architectures is still a major problem. Moreover, the software design and its development process needs improvements in order to support rapid-prototyping for ever changing system designs. Therefore, in this dissertation, we provide solutions for different problems faced in the development and deployment process of real-time systems. The contributions presented in this thesis enable efficient utilization of system resources, rapid design & development and component modularity & portability. In order to ease the certification process, time-triggered computation model is often used in distributed systems. However, time-triggered scheduling is NP-hard, due to which the process of schedule generation for complex large systems becomes convoluted. Large scheduler run-times and low scalability are two major problems with time-triggered scheduling. To solve these problems, we present a modular real-time scheduler based on a novel search-tree pruning technique, which consumes less time (compared to the state-of-the-art) in order to schedule tasks on large distributed time-triggered systems. In order to provide end-to-end guarantees, we also extend our modular scheduler to quickly generate schedules for time-triggered network traffic in large TTEthernet based networks. We evaluate our schedulers on synthetic but practical task-sets and demonstrate that our pruning technique efficiently reduces scheduler run-times and exhibits adequate scalability for future time-triggered distributed systems. In safety critical systems, the certification process also requires strict isolation between independent components. This isolation is enforced by utilizing resource partitioning approach, where different criticality components execute in different partitions (each temporally and spatially isolated from each other). However, existing partitioning approaches use periodic servers or tasks to service aperiodic activities. This approach leads to utilization loss and potentially leads to large latencies. On the contrary to the periodic approaches, state-of-the-art aperiodic task admission algorithms do not suffer from problems like utilization loss. However, these approaches do not support partitioned scheduling or mixed-criticality execution environment. To solve this problem, we propose an algorithm for online admission of aperiodic tasks which provides job execution flexibility, jitter control and leads to lower latencies of aperiodic tasks. For safety critical systems, fault-tolerance is one of the most important requirements. In time-triggered systems, modes are often used to ensure survivability against faults, i.e., when a fault is detected, current system configuration (or mode) is changed such that the overall system performance is either unaffected or degrades gracefully. In literature, it has been asserted that a task-set might be schedulable in individual modes but unschedulable during a mode-change. Moreover, conventional mode-change execution strategies might cause significant delays until the next mode is established. In order to address these issues, in this dissertation, we present an approach for schedulability analysis of mode-changes and propose mode-change delay reduction techniques in distributed system architecture defined by the DREAMS project. We evaluate our approach on an avionics use case and demonstrate that our approach can drastically reduce mode-change delays. In order to manage increasing system complexity, real-time applications also require new design and development technologies. Other than fulfilling the technical requirements, the main features required from such technologies include modularity and re-usability. AUTOSAR is one of these technologies in automotive industry, which defines an open standard for software architecture of a real-time operating system. However, being an industrial standard, the available proprietary tools do not support model extensions and/or new developments by third-parties and, therefore, hinder the software evolution. To solve this problem, we developed an open-source AUTOSAR toolchain which supports application development and code generation for several modules. In order to exhibit the capabilities of our toolchain, we developed two case studies. These case studies demonstrate that our toolchain generates valid artifacts, avoids dirty workarounds and supports application development. In order to cope with evolving system designs and hardware platforms, rapid-development of scheduling and analysis algorithms is required. In order to ease the process of algorithm development, a number of scheduling and analysis frameworks are proposed in literature. However, these frameworks focus on a specific class of applications and are limited in functionality. In this dissertation, we provide the skeleton of a scheduling and analysis framework for real-time systems. In order to support rapid-development, we also highlight different development components which promote code reuse and component modularity.

The authors explore the intrinsic trade-off in a DRAM between the power consumption (due to refresh) and the reliability. Their unique measurement platform allows tailoring to the design constraints depending on whether power consumption, performance or reliability has the highest design priority. Furthermore, the authors show how this measurement platform can be used for reverse engineering the internal structure of DRAMs and how this knowledge can be used to improve DRAM’s reliability.

The design of the fifth generation (5G) cellular network should take account of the emerging services with divergent quality of service requirements. For instance, a vehicle-to-everything (V2X) communication is required to facilitate the local data exchange and therefore improve the automation level in automated driving applications. In this work, we inspect the performance of two different air interfaces (i.e., LTE-Uu and PC5) which are proposed by the third generation partnership project (3GPP) to enable the V2X communication. With these two air interfaces, the V2X communication can be realized by transmitting data packets either over the network infrastructure or directly among traffic participants. In addition, the ultra-high reliability requirement in some V2X communication scenarios can not be fulfilled with any single transmission technology (i.e., either LTE-Uu or PC5). Therefore, we discuss how to efficiently apply multi-radio access technologies (multi-RAT) to improve the communication reliability. In order to exploit the multi-RAT in an efficient manner, both the independent and the coordinated transmission schemes are designed and inspected. Subsequently, the conventional uplink is also extended to the case where a base station can receive data packets through both the LTE-Uu and PC5 interfaces. Moreover, different multicast-broadcast single-frequency network (MBSFN) area mapping approaches are also proposed to improve the communication reliability in the LTE downlink. Last but not least, a system level simulator is implemented in this work. The simulation results do not only provide us insights on the performances of different technologies but also validate the effectiveness of the proposed multi-RAT scheme.

Die Einführung des Internets hat einen stetigen Wandel des täglichen, sowie beruflichen Alltags verursacht. Hierbei ist eine deutliche Verlagerung in den virtuellen Raum (Internet) festzustellen. Zusätzlich hat die Einführung von sozialen Netzwerken, wie beispielsweise Facebook das Verlangen des Nutzers immer „online“ zu sein, deutlich verstärkt. Hinzu kommen die kontinuierlich wachsenden Datenmengen, welche beispielsweise durch Videostreaming (YouTube oder Internet Protocol Television (IPTV)) oder den Austausch von Bildern verursacht werden. Zusätzlich verursachen neue Dienste, welche beispielsweise im Rahmen vom Internet der Dinge und auch Industrie 4.0 eingeführt werden, zusätzliche Datenmengen. Aktuelle Technologien wie Long Term Evolution Advanced (LTE-A) im Funkbereich und Very High Speed Digital Subsciber Line (VDSL) beziehungsweise Glasfaser in kabelgebundenen Netzen, versuchen diesen Anforderungen gerecht zu werden. Angesichts der steigenden Anforderungen an die Mobilität des Nutzers, ist die Verwendung von Funktechnologien unabdingbar. In Verbindung mit dem stetig wachsenden Datenaufkommen und den ansteigenden Datenraten ist ein wachsender Bedarf an Spektrum, also freien, beziehungsweise ungenutzten Frequenzbereichen einhergehend. Für die Identifikation geeigneter Bereiche müssen allerdings eine Vielzahl von Parametern und Einflussfaktoren betrachtet werden. Einer der entscheidenden Parameter ist die entstehende Dämpfung im betrachteten Frequenzbereich, da diese mit steigender Frequenz größer wird und somit die resultierende Abdeckung bei gleichbleibender Sendeleistung sinkt. In aktuellen Funksystemen werden Frequenzen < 6 GHz verwendet, da diese von den Ausbreitungseigenschaften geeignete Eigenschaften aufweisen. Des Weiteren müssen vorhandene Nutzungsrechte, Inhaber des Spektrums, Nutzungsbedingungen und so weiter im Vorfeld abgeklärt werden. In Deutschland wird die Koordination von der Bundesnetzagentur vorgenommen. Aufgrund der Vielfalt der vorhandenen Dienste und Anwendungen ist es leicht ersichtlich, dass der Frequenzbereich < 6 GHz stark ausgelastet ist. Neben den kontinuierlich ausgelasteten Diensten wie zum Beispiel Long Term Evolution (LTE) oder Digital Video Broadcast (DVB), gibt es spektrale Bereiche, die nur eine geringe zeitliche Auslastung aufweisen. Markant hierfür sind Frequenzbereiche, welche beispielsweise ausschließlich für militärische Nutzung reserviert sind. Bei genauerer Betrachtung fällt auf, dass sich dies nicht ausschließlich auf den zeitlichen Bereich beschränkt, vielmehr ergibt sich eine Kombination aus zeitlicher und räumlicher Beschränkung, da die Nutzung meist auf einen räumlichen Bereich eingrenzbar ist. Eine weitere Einschränkung resultiert aus der derzeit starren Vergabe von Frequenzbereichen. Die Zuteilung basiert auf langwierigen Antragsverfahren und macht somit eine kurzfristige variable Zuteilung unmöglich. Um diesem Problem gerecht zu werden, erfolgt im Rahmen dieser Arbeit die Entwicklung eines generischen Spektrum-Management-Systems (SMSs) zur dynamischen Zuteilung vorhandener Ressourcen. Eine Anforderung an das System ist die Unterstützung von bereits bekannten Spektrum Sharing Verfahren, wie beispielsweise Licensed Shared Access (LSA) beziehungsweise Authorized Shared Access (ASA) oder Spectrum Load Smoothing (SLS). Hierfür wird eine Analyse der derzeit bekannten Sharing Verfahren vorgenommen und diese bezüglich ihrer Anwendbarkeit charakterisiert. DesWeiteren werden die Frequenzbereiche unterhalb 6 GHz hinsichtlich ihrer Verwendbarkeiten und regulatorischen Anforderungen betrachtet. Zusätzlich wird ein erweiterter Anforderungskatalog an das Spektrum-Management-System (SMS) entwickelt, welcher als Grundlage für das Systemdesign verwendet wird. Essentiell ist hierbei, dass alle (potentiellen) Nutzer beziehungsweise Inhaber eines spektralen Bereiches die Funktionalität eines derartigen Systems verwenden können. Hieraus ergibt sich bereits die Anforderung der Skalierbarkeit des Systems. Zur Entwicklung einer geeigneten Systemarchitektur werden bereits vorhandene Lösungsansätze zur Verwaltung und Speicherung von Daten hinsichtlich ihrer Anwendbarkeit verglichen und bewertet. Des Weiteren erfolgt die Einbeziehung der geografischen Position. Um dies adäquat gewährleisten zu können, werden hierarchische Strukturen in Netzwerken untersucht und auf ihre Verwendbarkeit geprüft. Das Ziel dieser Arbeit ist die Entwicklung eines Spektrum-Management- Systems (SMSs) durch Adaption bereits vorhandener Technologien und Verfahren, sowie der Berücksichtigung aller definierten Anforderungen. Es hat sich gezeigt, dass die Verwendung einer zentralisierten Broker- Lösung nicht geeignet ist, da die Verzögerungszeit einen exponentiellförmigen Verlauf bezüglich der Anzahl der Anfragen aufweist und somit nicht skaliert. Dies kann mittels einer Distributed Hash Table (DHT)- basierten Erweiterung überwunden werden ohne dabei die Funktionalität der Broker-Lösung einzuschränken. Für die Einbringung der Geoinformation hat sich die hierarchische Struktur, vergleichbar zum Domain Naming Service (DNS) als geeignet erwiesen. Als Parameter für die Evaluierung hat sich die resultierende Zugriffszeit, das heißt die Zeit welche das System benötigt um Anfragen zu bearbeiten, sowie die resultierende Anzahl der versorgbaren Nutzer herausgestellt. Für die Simulation wird ein urbanes Areal mit fünf Gebäuden betrachtet. In der Mitte befindet sich ein sechsstöckiges Firmengebäude, welches in jedem Stockwerk mit einem Wireless Local Area Network Access Point (WLAN-AP) ausgestattet ist. Umliegend befinden sich vier Privathäuser, welche jeweils mit einem WLAN-AP ausgestattet sind. Das komplette Areal wird von drei Mobilfunkbetreibern mit je einer Basisstation (BS) versorgt. Als Ausgangspunkt für die Evaluierung erfolgt der Betrieb ohne SMS. Aus den Ergebnissen wird deutlich, dass eine Überlastung der Long Term Evolution Basisstationen (LTE-BSen) vorliegt (im Speziellen bei Betreiber A und B). Im zweiten Durchlauf wird das Szenario mit einem SMS betrachtet. Zusätzlich kommen in diesem Fall noch Mikro Basisstationen (Mikro-BSen) zum Einsatz, welche von der Spezifikation vergleichbar zu einem Wireless Local Area Network (WLAN) sind. Hier zeigt sich ein deutlich ausgewogeneres Systemverhalten. Alle BSen und Access Points (APs) befinden sich deutlich unterhalb der Volllastgrenze. Die Untersuchungen im Rahmen dieser Arbeit belegen, dass ein heterogenes, zeitweise überlastetes Funksystem, vollständig harmonisiert werden kann. Des Weiteren ermöglicht der Einsatz eines SMSs die effiziente Verwendung von temporär ungenutzten Frequenzbereichen (sogenannte White- und Gray-spaces).

Durch die stetige Zunahme von dezentralen Erzeugungsanlagen, den anstehenden Smart-Meter Rollout sowie die zu erwartende Elektrifizierung des Verkehrssektors (E-Mobilität) steht die Netzplanung und Netzbetriebsführung von Niederspannungsnetzen (NS-Netzen) in Deutschland vor großen Herausforderungen. In den letzten Jahren wurden daher viele Studien, Forschungs- und Demonstrationsprojekte zu den oben genannten Themen durchge-führt und die Ergebnisse sowie die entwickelten Methoden publiziert. Jedoch lassen sich die publizierten Methoden meist nicht nachbilden bzw. validieren, da die Untersuchungsmodelle oder die angesetzten Szenarien für Dritte nicht nachvollziehbar sind. Es fehlen einheitliche Netzmodelle, die die deutschen NS-Netze abbilden und für Ver-gleichsuntersuchungen herangezogen werden können, ähnlich dem Beispiel der nordamerikanischen Verteilnetzmodelle des IEEE. Im Gegensatz zum Übertragungsnetz, dessen Struktur hinreichend genau bekannt ist, sind passende Netzmodelle für NS-Netze wegen der hohen Anzahlen der NS-Netze und Verteilnetzbetreiber (VNB) nur schwer abzubilden. Des Weiteren ist eine detaillierte Darstellung realer NS-Netze in wissenschaftlichen Publikationen aus daten-schutzrechtlichen Gründen meist nicht erwünscht. Für Untersuchungen im Rahmen eines Forschungsprojekts wurden darum möglichst charakteristische synthetische NS-Netzmodelle erstellt, die sich an gängigen deutschen Siedlungsstrukturen und üblichen Netzplanungsgrundsätzen orientieren. In dieser Arbeit werden diese NS-Netzmodelle sowie ihre Entwicklung im Detail erklärt. Damit stehen erstmals für die Öffentlichkeit nachvollziehbare NS-Netzmodelle für den deutschsprachigen Raum zur Verfügung. Sie können als Benchmark für wissenschaftliche Untersuchungen sowie zur Methodenentwicklung verwendet werden.

”In contemporary electronics 80% of a chip may perform digital functions but the 20% of analog functions may take 80% of the development time.” [1]. Aggravating this, the demands on analog design is increasing with rapid technology scaling. Most designs have moved away from analog to digital domains, where possible, however, interacting with the environment will always require analog to digital data conversion. Adding to this problem, the number of sensors used in consumer and industry related products are rapidly increasing. Designers of ADCs are dealing with this problem in several ways, the most important is the migration towards digital designs and time domain techniques. Time to Digital Converters (TDC) are becoming increasingly popular for robust signal processing. Biological neurons make use of spikes, which carry spike timing information and will not be affected by the problems related to technology scaling. Neuromorphic ADCs still remain exotic with few implementations in sub-micron technologies Table 2.7. Even among these few designs, the strengths of biological neurons are rarely exploited. From a previous work [2], LUCOS, a high dynamic range image sensor, the efficiency of spike processing has been validated. The ideas from this work can be generalized to make a highly effective sensor signal conditioning system, which carries the promise to be robust to technology scaling. The goal of this work is to create a novel spiking neural ADC as a novel form of a Multi-Sensor Signal Conditioning and Conversion system, which • Will be able to interface with or be a part of a System on Chip with traditional analog or advanced digital components. • Will have a graceful degradation. • Will be robust to noise and jitter related problems. • Will be able to learn and adapt to static errors and dynamic errors. • Will be capable of self-repair, self-monitoring and self-calibration Sensory systems in humans and other animals analyze the environment using several techniques. These techniques have been evolved and perfected to help the animal sur- vive. Different animals specialize in different sense organs, however, the peripheral neural network architectures remain similar among various animal species with few ex- ceptions. While there are many biological sensing techniques present, most popularly used engineering techniques are based on intensity detection, frequency detection, and edge detection. These techniques are used with traditional analog processing (e.g., colorvi sensors using filters), and with biological techniques (e.g. LUCOS chip [2]). The local- ization capability of animals has never been fully utilized. One of the most important capabilities for animals, vertebrates or invertebrates, is the capability for localization. The object of localization can be predator, prey, sources of water, or food. Since these are basic necessities for survival, they evolve much faster due to the survival of the fittest. In fact, localization capabilities, even if the sensors are different, have convergently evolved to have same processing methods (coincidence detection) in their peripheral neurons (for e.g., forked tongue of a snake, antennae of a cockroach, acoustic localization in fishes and mammals). This convergent evolution increases the validity of the technique. In this work, localization concepts based on acoustic localization and tropotaxis are investigated and employed for creation of novel ADCs. Unlike intensity and frequency detection, which are not linear (for e.g. eyes saturate in bright light, loose color perception in low light), localization is inherently linear. This is mainly because the accurate localization of predator or prey can be the difference between life and death for an animal. Figure 1 visually explains the ADC concept proposed in this work. This has two parts. (1) Sensor to Spike(time) Conversion (SSC), (2) Spike(time) to Digital Conversion(SDC). Both of the structures have been designed with models of biological neurons. The combination of these two structures is called SSDC. To efficiently implement the proposed concept, a comparison of several biological neural models is made and two models are shortlisted. Various synapse structures are also studied. From this study, Leaky Integrate and Fire neuron (LIF) is chosen since it fulfills all the requirements of the proposed structure. The analog neuron and synapse designs from Indiveri et. al. [3], [4] were taken, and simulations were conducted using cadence and the behavioral equivalence with biological counterpart was checked. The LIF neuron had features, that were not required for the proposed approach. A simple LIF neuron stripped of these features and was designed to be as fast as allowed by the technology. The SDC was designed with the neural building blocks and the delays were designed using buffer chains. This SDC converts incoming Time Interval Code (TIC) to sparse place coding using coincidence detection. Coincidence detection is a property of spiking neurons, which is a time domain equivalent of a Gaussian Kernel. The SDC is designed to have an online reconfigurable Gaussian kernel width, weight, threshold, and refractory period. The advantage of sparse place codes, which contain rank order coding wasvii Figure 1: ADC as a localization problem (right), Jeffress model of sound localization visualized (left). The values t 1 and t 2 indicate the time taken from the source to s1 and s2 respectively. described in our work [5]. A time based winner take all circuit with memory was created based on a previous work [6] for reading out of sparse place codes asynchronously. The SSC was also initially designed with the same building blocks. Additionally, a differential synapse was designed for better SSC. The sensor element considered wasviii a Wheatstone full bridge AMR sensor AFF755 from Sensitec GmbH. A reconfigurable version of the synapse was also designed for a more generic sensor interface. The first prototype chip SSDCα was designed with 257 modules of coincidence detectors realizing the SDC and the SSC. Since the spike times are the most important information, the spikes can be treated as digital pulses. This provides the capability for digital communication between analog modules. This creates a lot of freedom for use of digital processing between the discussed analog modules. This advantage is fully exploited in the design of SSDCα. Three SSC modules are multiplexed to the SDC. These SSC modules also provide outputs from the chip simultaneously. A rising edge detecting fixed pulse width generation circuit is used to create pulses that are best suited for efficient performance of the SDC. The delay lines are made reconfigurable to increase robustness and modify the span of the SDC. The readout technique used in the first prototype is a relatively slow but safe shift register. It is used to analyze the characteristics of the core work. This will be replaced by faster alternatives discussed in the work. The area of the chip is 8.5 mm 2 . It has a sampling rate from DC to 150 kHz. It has a resolution from 8-bit to 13-bit. It has 28,200 transistors on the chip. It has been designed in 350 nm CMOS technology from ams. The chip has been manufactured and tested with a sampling rate of 10 kHz and a theoretical resolution of 8 bits. However, due to the limitations of our Time-Interval-Generator, we are able to confirm for only 4 bits of resolution. The key novel contributions of this work are • Neuromorphic implementation of AD conversion as a localization problem based on sound localization and tropotaxis concepts found in nature. • Coincidence detection with sparse place coding to enhance resolution. • Graceful degradation without redundant elements, inherent robustness to noise, which helps in scaling of technologies • Amenable to local adaptation and self-x features. Conceptual goals have all been fulfilled, with the exception of adaptation. The feasibility for local adaptation has been shown with promising results and further investigation is required for future work. This thesis work acts as a baseline, paving the way for R&D in a new direction. The chip design has used 350 nm ams hitkit as a vehicle to prove the functionality of the core concept. The concept can be easily ported to present aggressively-scaled-technologies and future technologies.

Advanced sensing systems, sophisticated algorithms, and increasing computational resources continuously enhance the advanced driver assistance systems (ADAS). To date, despite that some vehicle based approaches to driver fatigue/drowsiness detection have been realized and deployed, objectively and reliably detecting the fatigue/drowsiness state of driver without compromising driving experience still remains challenging. In general, the choice of input sensorial information is limited in the state-of-the-art work. On the other hand, smart and safe driving, as representative future trends in the automotive industry worldwide, increasingly demands the new dimensional human-vehicle interactions, as well as the associated behavioral and bioinformatical data perception of driver. Thus, the goal of this research work is to investigate the employment of general and custom 3D-CMOS sensing concepts for the driver status monitoring, and to explore the improvement by merging/fusing this information with other salient customized information sources for gaining robustness/reliability. This thesis presents an effective multi-sensor approach with novel features to driver status monitoring and intention prediction aimed at drowsiness detection based on a multi-sensor intelligent assistance system -- DeCaDrive, which is implemented on an integrated soft-computing system with multi-sensing interfaces in a simulated driving environment. Utilizing active illumination, the IR depth camera of the realized system can provide rich facial and body features in 3D in a non-intrusive manner. In addition, steering angle sensor, pulse rate sensor, and embedded impedance spectroscopy sensor are incorporated to aid in the detection/prediction of driver's state and intention. A holistic design methodology for ADAS encompassing both driver- and vehicle-based approaches to driver assistance is discussed in the thesis as well. Multi-sensor data fusion and hierarchical SVM techniques are used in DeCaDrive to facilitate the classification of driver drowsiness levels based on which a warning can be issued in order to prevent possible traffic accidents. The realized DeCaDrive system achieves up to 99.66% classification accuracy on the defined drowsiness levels, and exhibits promising features such as head/eye tracking, blink detection, gaze estimation that can be utilized in human-vehicle interactions. However, the driver's state of "microsleep" can hardly be reflected in the sensor features of the implemented system. General improvements on the sensitivity of sensory components and on the system computation power are required to address this issue. Possible new features and development considerations for DeCaDrive are discussed as well in the thesis aiming to gain market acceptance in the future.

In current practices of system-on-chip (SoC) design a trend can be observed to integrate more and more low-level software components into the system hardware at different levels of granularity. The implementation of important control functions and communication structures is frequently shifted from the SoC’s hardware into its firmware. As a result, the tight coupling of hardware and software at a low level of granularity raises substantial verification challenges since the conventional practice of verifying hardware and software independently is no longer sufficient. This calls for new methods for verification based on a joint analysis of hardware and software. This thesis proposes hardware-dependent models of low-level software for performing formal verification. The proposed models are conceived to represent the software integrated with its hardware environment according to the current SoC design practices. Two hardware/software integration scenarios are addressed in this thesis, namely, speed-independent communication of the processor with its hardware periphery and cycle-accurate integration of firmware into an SoC module. For speed-independent hardware/software integration an approach for equivalence checking of hardware-dependent software is proposed and an evaluated. For the case of cycle-accurate hardware/software integration, a model for hardware/software co-verification has been developed and experimentally evaluated by applying it to property checking.

To continue reducing voltage in scaled technologies, both circuit and architecture-level resiliency techniques are needed to tolerate process-induced defects, variation, and aging in SRAM cells. Many different resiliency schemes have been proposed and evaluated, but most prior results focus on voltage reduction instead of energy reduction. At the circuit level, device cell architectures and assist techniques have been shown to lower Vmin for SRAM, while at the architecture level, redundancy and cache disable techniques have been used to improve resiliency at low voltages. This paper presents a unified study of error tolerance for both circuit and architecture techniques and estimates their area and energy overheads. Optimal techniques are selected by evaluating both the error-correcting abilities at low supplies and the overheads of each technique in a 28nm. The results can be applied to many of the emerging memory technologies.

Magnetic spin-based memory technologies are a promising solution to overcome the incoming limits of microelectronics. Nevertheless, the long write latency and high write energy of these memory technologies compared to SRAM make it difficult to use these for fast microprocessor memories, such as L1- Caches. However, the recent advent of the Spin Orbit Torque (SOT) technology changed the story: indeed, it potentially offers a writing speed comparable to SRAM with a much better density as SRAM and an infinite endurance, paving the way to a new paradigm in processor architectures, with introduction of non- volatility in all the levels of the memory hierarchy towards full normally-off and instant-on processors. This paper presents a full design flow, from device to system, allowing to evaluate the potential of SOT for microprocessor cache memories and very encouraging simulation results using this framework.