C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS (J.7)
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With the growing support for features such as hardware virtualization tied to the boost of hardware capacity, embedded systems are now able to regroup many software components on a same hardware platform to save costs. This evolution has raised system complexity, motivating the introduction of Mixed-Criticality Systems (MCS) to consolidate applications from different criticality levels on a hardware target: in critical environments such as an aircraft or a factory floor, high-critical functions are now regrouped with other non-critical functions. A key requirement of such system is to guarantee that the execution of a critical function cannot be compromised by other functions, especially by ones with a lower-criticality level. In this context, runtime intrusion detection contributes to secure system execution to avoid an intentional misbehavior in critical applications.
Host Intrusion Detection Systems (HIDS) has been an active field of research for computer security for more than two decades. The goal of HIDS is to detect traces of malicious activity in the execution of a monitored software at runtime. While this topic has been extensively investigated for general-purpose computers, its application in the specific context of embedded MCS is comparatively more recent.
We extend the domain of HIDS research towards HIDS deployment into industrial embedded MCS. For this, we provide a review of state-of-the-art HIDS solutions and evaluate the main problems towards a deployment into an industrial embedded MCS.
We present several HIDS approaches based on solutions for general-purpose computers, which we apply to protect the execution of an application running into an embedded MCS. We introduce two main HIDS methods to protect the execution of a given user-level application. Because of possible criticality constraints of the monitored application, such as industrial certification aspects, our solutions support transparent monitoring; i.e. they do not require application instrumentation. On one hand, we propose a machine-learning (ML) based framework to monitor low-level system events transparently. On the other hand, we introduce a hardware-assisted control-flow monitoring framework to deploy control-flow integrity monitoring without instrumentation of the monitored application.
We provide a methodology to integrate and evaluate HIDS mechanisms into an embedded MCS. We evaluate and implement our monitoring solutions on a practical industrial platform, using generic hardware system and SYSGO’s industrial real-time hypervisor.
Hardware Contention-Aware Real-Time Scheduling on Multi-Core Platforms in Safety-Critical Systems
(2019)
While the computing industry has shifted from single-core to multi-core processors for performance gain, safety-critical systems (SCSs) still require solutions that enable their transition while guaranteeing safety, requiring no source-code modifications and substantially reducing re-development and re-certification costs, especially for legacy applications that are typically substantial. This dissertation considers the problem of worst-case execution time (WCET) analysis under contentions when deadline-constrained tasks in independent partitioned task set execute on a homogeneous multi-core processor with dynamic time-triggered shared memory bandwidth partitioning in SCSs.
Memory bandwidth in multi-core processors is shared across cores and is a significant cause of performance bottleneck and temporal variability of multiple-orders in task’s execution times due to contentions in memory sub-system. Further, the circular dependency is not only between WCET and CPU scheduling of others cores, but also between WCET and memory bandwidth assignments over time to cores. Thus, there is need of solutions that allow tailoring memory bandwidth assignments to workloads over time and computing safe WCET. It is pragmatically infeasible to obtain WCET estimates from static WCET analysis tools for multi-core processors due to the sheer computational complexity involved.
We use synchronized periodic memory servers on all cores that regulate each core’s maximum memory bandwidth based on allocated bandwidth over time. First, we present a workload schedulability test for known even-memory-bandwidth-assignment-to-active-cores over time, where the number of active cores represents the cores with non-zero memory bandwidth assignment. Its computational complexity is similar to merge-sort. Second, we demonstrate using a real avionics certified safety-critical application how our method’s use can preserve an existing application’s single-core CPU schedule under contentions on a multi-core processor. It enables incremental certification using composability and requires no-source code modification.
Next, we provide a general framework to perform WCET analysis under dynamic memory bandwidth partitioning when changes in memory bandwidth to cores assignment are time-triggered and known. It provides a stall maximization algorithm that has a complexity similar to a concave optimization problem and efficiently implements the WCET analysis. Last, we demonstrate dynamic memory assignments and WCET analysis using our method significantly improves schedulability compared to the stateof-the-art using an Integrated Modular Avionics scenario.
In its rather short history robotic research has come a long way in the half century since it started to exist as a noticeable scientic eld. Due to its roots in engineering, computer science, mathematics, and several other 'classical' scientic branches,a grand diversity of methodologies and approaches existed from the very beginning. Hence, the researchers in this eld are in particular used to adopting ideas that originate in other elds. As a fairly logical consequence of this, scientists tended to biology during the 1970s in order to nd approaches that are ideally adapted to the conditions of our natural environment. Doing so allows for introducing principles to robotics that have already shown their great potential by prevailing in a tough evolutionary selection process for millions of years. The variety of these approaches spans from efficient locomotion, to sensor processing methodologies and all the way to control architectures. Thus, the full spectrum of challenges for autonomous interaction with the surroundings while pursuing a task can be covered by such means. A feature that has proven to be amongst the most challenging to recreate is the human ability of biped locomotion. This is mainly caused by the fact that walking,running and so on are highly complex processes involving the need for energy efficient actuation, sophisticated control architectures and algorithms, and an elaborate mechanical design while at the same time posting restrictions concerning stability and weight. However, it is of special interest since our environment is favoring this specic kind of locomotion and thus promises to open up an enormous potential if mastered. More than the mere scientic interest, it is the fascination of understanding and recreating parts of oneself that drives the ongoing eorts in this area of research. The fact that this is not at all an easy task to tackle is not only caused by the highly dynamical processes but also has its roots in the challenging design process. That is because it cannot be limited to just one aspect like e.g. the control architecture, actuation, sensors, or mechanical design alone. Each aspect has to be incorporated into a sound general concept in order to allow for a successful outcome in the end. Since control is in this context inseparably coupled with the mechanics of the system, both has to be dealt with here.