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Embedded ECC Solutions for Emerging Memories (PCMs)

  • Emerging Memories (EMs) could benefit from Error Correcting Codes (ECCs) able to correct few errors in a few nanoseconds. The low latency is necessary to meet the DRAM- like and/or eXecuted-in-Place requirements of Storage Class Memory devices. The error correction capability would help manufacturers to cope with unknown failure mechanisms and to fulfill the market demand for a rapid increase in density. This paper shows the design of an ECC decoder for a shortened BCH code with 256-data-bit page able to correct three errors in less than 3 ns. The tight latency constraint is met by pre-computing the coefficients of carefully chosen Error Locator Polynomials, by optimizing the operations in the Galois Fields and by resorting to a fully parallel combinatorial implementation of the decoder. The latency and the area occupancy are first estimated by the number of elementary gates to traverse, and by the total number of elementary gates of the decoder. Eventually, the implementation of the solution by Synopsys topographical synthesis methodology in 54nm logic gate length CMOS technology gives a latency lower than 3 ns and a total area less than \(250 \cdot 10^3 \mu m^2\).

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Verfasserangaben:M. Ferrari, A. Tomasoni, S. Bellini, P. Amato, M. Sforzin, C. Laurent
URN (Permalink):urn:nbn:de:hbz:386-kluedo-43206
Dokumentart:Konferenzveröffentlichung
Sprache der Veröffentlichung:Englisch
Veröffentlichungsdatum (online):18.03.2016
Jahr der Veröffentlichung:2016
Veröffentlichende Institution:Technische Universität Kaiserslautern
Datum der Publikation (Server):14.03.2016
Freies Schlagwort / Tag:DRAM; Emerging Memories; Error Correction Codes; Flash Memories; Storage Class Memories
Seitenzahl:6
Fachbereiche / Organisatorische Einheiten:Fachbereich Elektrotechnik und Informationstechnik
CCS-Klassifikation (Informatik):B. Hardware / B.3 MEMORY STRUCTURES / B.3.0 General
DDC-Sachgruppen:6 Technik, Medizin, angewandte Wissenschaften / 621.3 Elektrontechnik, Elektronik
Sammlungen:International Workshop on Emerging Memory Solutions
Lizenz (Deutsch):Standard gemäß KLUEDO-Leitlinien vom 30.07.2015