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Architecture Evaluation Tool for 3D CAMs
- Three-dimensional (3D) integration using through- silicon via (TSV) has been used for memory designs. Content addressable memory (CAM) is an important component in digital systems. In this paper, we propose an evaluation tool for 3D CAMs, which can aid the designer to explore the delay and power of various partitioning strategies. Delay, power, and energy models of 3D CAM with respect to different architectures are built as well.
| Author: | Yong-Xiao Chen, Jin-Fu Li |
|---|---|
| URN: | urn:nbn:de:hbz:386-kluedo-43279 |
| Document Type: | Conference Proceeding |
| Language of publication: | English |
| Publication Date: | 2016/03/18 |
| Year of Publication: | 2016 |
| Publishing Institute: | Technische Universität Kaiserslautern |
| Date of the Publication (Server): | 2016/03/14 |
| Tag: | CAM |
| Number of page: | 2 |
| Faculties / Organisational entities: | Fachbereich Elektrotechnik und Informationstechnik |
| CCS-Classification (computer science): | B. Hardware / B.3 MEMORY STRUCTURES / B.3.2 Design Styles (D.4.2) / Associative memories |
| DDC-Cassification: | 6 Technik, Medizin, angewandte Wissenschaften / 621.3 Elektrotechnik, Elektronik |
| Collections: | International Workshop on Emerging Memory Solutions |
| Licence (German): |  Standard gemäß KLUEDO-Leitlinien vom 30.07.2015 |
