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AXI4-Stream Upsizing/Downsizing Data Width Converters for Hardware-In-the-Loop Simulations

  • Hardware prototyping is an essential part in the hardware design flow. Furthermore, hardware prototyping usually relies on system-level design and hardware-in-the-loop simulations in order to develop, test and evaluate intellectual property cores. One common task in this process consist on interfacing cores with different port specifications. Data width conversion is used to overcome this issue. This work presents two open source hardware cores compliant with AXI4-Stream bus protocol, where each core performs upsizing/downsizing data width conversion.
Metadaten
Author:Luis Vega, Philipp Schläfer, Christian de Schryver
URN (permanent link):urn:nbn:de:hbz:386-kluedo-34903
Document Type:Article
Language of publication:English
Publication Date:2013/04/22
Year of Publication:2013
Publishing Institute:Technische Universität Kaiserslautern
Date of the Publication (Server):2013/04/23
Tag:AXI4-Stream; Data width converter
Downsizing/Upsizing
GND-Keyword:FPGA; Hardware-in-the-loop; Streaming
Faculties / Organisational entities:Fachbereich Elektrotechnik und Informationstechnik
DDC-Cassification:6 Technik, Medizin, angewandte Wissenschaften / 620 Ingenieurwissenschaften und Maschinenbau
Licence (German):Standard gemäß KLUEDO-Leitlinien vom 10.09.2012