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VMEbus Controller Synthesis by Communicating Asynchronous Sequential Circuits

  • This paper presents the systematic synthesis of a fairly complex digitalcircuit and its CPLD implementation as an assemblage of communicatingasynchronous sequential circuits. The example, a VMEbus controller, waschosen because it has to control concurrent processes and to arbitrateconflicting requests.

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Metadaten
Author:Wilfried Eisele, Gernot Eckstein, Jochen Beister
URN (permanent link):urn:nbn:de:hbz:386-kluedo-30
Document Type:Preprint
Language of publication:English
Year of Completion:1994
Year of Publication:1994
Publishing Institute:Technische Universität Kaiserslautern
Date of the Publication (Server):2000/04/03
Tag:CPLD; Petri nets; VMEbus; asynchronous circuits; bus controller
Faculties / Organisational entities:Fachbereich Elektrotechnik und Informationstechnik
DDC-Cassification:6 Technik, Medizin, angewandte Wissenschaften / 620 Ingenieurwissenschaften und Maschinenbau
Licence (German):Standard gemäß KLUEDO-Leitlinien vor dem 27.05.2011