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A Case for Near Memory Computation Inside the Smart Memory Cube

  • 3D integration of solid-state memories and logic, as demonstrated by the Hybrid Memory Cube (HMC), offers major opportunities for revisiting near-memory computation and gives new hope to mitigate the power and performance losses caused by the “memory wall”. In this paper we present the first exploration steps towards design of the Smart Memory Cube (SMC), a new Processor-in-Memory (PIM) architecture that enhances the capabilities of the logic-base (LoB) in HMC. An accurate simulation environment has been developed, along with a full featured software stack. All offloading and dynamic overheads caused by the operating system, cache coherence, and memory management are considered, as well. Benchmarking results demonstrate up to 2X performance improvement in comparison with the host SoC, and around 1.5X against a similar host-side accelerator. Moreover, by scaling down the voltage and frequency of PIM’s processor it is possible to reduce energy by around 70% and 55% in comparison with the host and the accelerator, respectively.

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Metadaten
Author:Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
URN (permanent link):urn:nbn:de:hbz:386-kluedo-43241
Document Type:Conference Proceeding
Language of publication:English
Publication Date:2016/03/18
Year of Publication:2016
Publishing Institute:Technische Universität Kaiserslautern
Date of the Publication (Server):2016/03/14
Tag:HMC; Near Memory Computation; PIM; Smart Memory Cube
Number of page:2
Faculties / Organisational entities:Fachbereich Elektrotechnik und Informationstechnik
CCS-Classification (computer science):B. Hardware / B.3 MEMORY STRUCTURES / B.3.2 Design Styles (D.4.2) / Primary memory
DDC-Cassification:6 Technik, Medizin, angewandte Wissenschaften / 621.3 Elektrontechnik, Elektronik
Collections:International Workshop on Emerging Memory Solutions
Licence (German):Standard gemäß KLUEDO-Leitlinien vom 30.07.2015