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RAPIDO Testing of Assisted Write and Read operations for SRAMs

  • Lowering the supply voltage of Static Random-Access Memories (SRAM) is key to reduce power consumption, however since this badly affects the circuit performances, it might lead to various forms of loss of functionality. In this work, we present silicon results showing significant yield improvement, achieved with write and read assist techniques on a 6T high- density bitcell manufactured in 40 nm technology. Data is successfully modeled with an original spice-based method that allows reproducing at high computing efficiency the effects of static negative bitline write assist, the effects of static wordline underdrive read assist, while the effects of read ability losses due to low-voltage operations on the yield are not taken into account in the model.

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Metadaten
Author:J. Nguyen, D. Turgis, D. Bonciani, B. Lhomme, Y. Carminati, O. Callen, G. Guirleo, L. Ciampolini, G. Ghibaudo
URN (permanent link):urn:nbn:de:hbz:386-kluedo-43299
Document Type:Conference Proceeding
Language of publication:English
Publication Date:2016/03/18
Year of Publication:2016
Publishing Institute:Technische Universität Kaiserslautern
Date of the Publication (Server):2016/03/14
Tag:SRAM; half-selected cell; negative bit line; read assist; wordline underdrive; write assist; write margin; yield
Number of page:4
Faculties / Organisational entities:Fachbereich Elektrotechnik und Informationstechnik
CCS-Classification (computer science):B. Hardware / B.3 MEMORY STRUCTURES / B.3.1 Semiconductor Memories (NEW) (B.7.1) / Static memory (SRAM) (NEW)
DDC-Cassification:6 Technik, Medizin, angewandte Wissenschaften / 621.3 Elektrontechnik, Elektronik
Collections:International Workshop on Emerging Memory Solutions
Licence (German):Standard gemäß KLUEDO-Leitlinien vom 30.07.2015