TY  - INPR
A1  - Eisele, Wilfried
A1  - Eckstein, Gernot
A1  - Beister, Jochen
T1  - VMEbus Controller Synthesis by Communicating Asynchronous Sequential Circuits
N2  - This paper presents the systematic synthesis of a fairly complex digitalcircuit and its CPLD implementation as an assemblage of communicatingasynchronous sequential circuits. The example, a VMEbus controller, waschosen because it has to control concurrent processes and to arbitrateconflicting requests.
KW  - asynchronous circuits
KW  - VMEbus
KW  - bus controller
KW  - CPLD
KW  - Petri nets
Y1  - 1994
UR  - https://kluedo.ub.uni-kl.de/frontdoor/index/index/docId/29
UR  - https://nbn-resolving.org/urn:nbn:de:hbz:386-kluedo-30
ER  -