TY - CONF
A1 - Ferrari, M.
A1 - Tomasoni, A.
A1 - Bellini, S.
A1 - Amato, P.
A1 - Sforzin, M.
A1 - Laurent, C.
T1 - Embedded ECC Solutions for Emerging Memories (PCMs)
N2 - Emerging Memories (EMs) could benefit from Error Correcting Codes (ECCs) able to correct few errors in a few nanoseconds. The low latency is necessary to meet the DRAM- like and/or eXecuted-in-Place requirements of Storage Class Memory devices. The error correction capability would help manufacturers to cope with unknown failure mechanisms and to fulfill the market demand for a rapid increase in density. This paper shows the design of an ECC decoder for a shortened BCH code with 256-data-bit page able to correct three errors in less than 3 ns. The tight latency constraint is met by pre-computing the coefficients of carefully chosen Error Locator Polynomials, by optimizing the operations in the Galois Fields and by resorting to a fully parallel combinatorial implementation of the decoder. The latency and the area occupancy are first estimated by the number of elementary gates to traverse, and by the total number of elementary gates of the decoder. Eventually, the implementation of the solution by Synopsys topographical synthesis methodology in 54nm logic gate length CMOS technology gives a latency lower than 3 ns and a total area less than \(250 \cdot 10^3 \mu m^2\).
KW - Error Correction Codes
KW - Flash Memories
KW - DRAM
KW - Emerging Memories
KW - Storage Class Memories
Y1 - 2016
UR - https://kluedo.ub.uni-kl.de/frontdoor/index/index/docId/4320
UR - https://nbn-resolving.org/urn:nbn:de:hbz:386-kluedo-43206
ER -